diff --git a/cpu/ppc4xx/405gp_enet.c b/cpu/ppc4xx/405gp_enet.c
index b7b03ed..9639c92 100644
--- a/cpu/ppc4xx/405gp_enet.c
+++ b/cpu/ppc4xx/405gp_enet.c
@@ -218,10 +218,10 @@
 	/* AS.HARNOIS
 	 * We should have :
 	 * packetHandled <=  packetReceived <= packetHandled+PKTBUFSRX
-         * In the most cases packetHandled = packetReceived, but it
-         * is possible that new packets (without relationship with
-         * current transfer) have got the time to arrived before
-         * netloop calls eth_halt
+	 * In the most cases packetHandled = packetReceived, but it
+	 * is possible that new packets (without relationship with
+	 * current transfer) have got the time to arrived before
+	 * netloop calls eth_halt
 	 */
 	printf ("About preceeding transfer:\n"
 		"- Sent packet number %d\n"
@@ -251,8 +251,8 @@
 	tx_u_index = 0;			/* Transmit User Queue Index */
 
 #if defined(CONFIG_440)
-        /* set RMII mode */
-        out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
+	/* set RMII mode */
+	out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
 #endif /* CONFIG_440 */
 
 	/* EMAC RESET */
@@ -426,8 +426,8 @@
 	/* set receive  low/high water mark register */
 #if defined(CONFIG_440)
 	/* 440GP has a 64 byte burst length */
-        out32 (EMAC_RX_HI_LO_WMARK, 0x80009000);
-        out32 (EMAC_TXM1,           0xf8640000);
+	out32 (EMAC_RX_HI_LO_WMARK, 0x80009000);
+	out32 (EMAC_TXM1,           0xf8640000);
 #else /* CONFIG_440 */
 	/* 405s have a 16 byte burst length */
 	out32 (EMAC_RX_HI_LO_WMARK, 0x0f002000);
@@ -530,8 +530,8 @@
 		/* loop until either TINT turns on or 3 seconds elapse */
 		if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
 			/* transmit is done, so now check for errors
-                         * If there is an error, an interrupt should
-                         * happen when we return
+			 * If there is an error, an interrupt should
+			 * happen when we return
 			 */
 			time_now = get_timer (0);
 			if ((time_now - time_start) > 3000) {
@@ -568,16 +568,16 @@
 		my_uic1msr = mfdcr (uic1msr);
 
 		if (!(my_uic0msr & UIC_MRE)
-                    && !(my_uic1msr & (UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE))) {
-                        /* not for us */
+		    && !(my_uic1msr & (UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE))) {
+			/* not for us */
 			return (rc);
 		}
 
 		/* get and clear controller status interrupts */
 		/* look at Mal and EMAC interrupts */
 		if ((my_uic0msr & UIC_MRE)
-                    || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
-                        /* we have a MAL interrupt */
+		    || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
+			/* we have a MAL interrupt */
 			mal_isr = mfdcr (malesr);
 			/* look for mal error */
 			if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
@@ -595,7 +595,7 @@
 			}
 		}
 		if ((emac_ier & emac_isr)
-                    || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
+		    || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
 			mtdcr (uic0sr, UIC_MRE); /* Clear */
 			mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
 			return (rc);		/* we had errors so get out */
@@ -614,8 +614,8 @@
 				rc = 0;
 			}
 		}
-                mtdcr (uic0sr, UIC_MRE); /* Clear */
-                mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
+		mtdcr (uic0sr, UIC_MRE); /* Clear */
+		mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
 	} while (serviced);
 
 	return (rc);
@@ -866,42 +866,42 @@
 #if defined(CONFIG_NET_MULTI)
 int ppc_4xx_eth_initialize(bd_t *bis)
 {
-        struct eth_device *dev;
-        int                eth_num = 0;
+	struct eth_device *dev;
+	int                eth_num = 0;
 
-        dev = malloc (sizeof *dev);
-        if (dev == NULL) {
-                printf(__FUNCTION__ ": Cannot allocate eth_device\n");
-                return (-1);
-        }
+	dev = malloc (sizeof *dev);
+	if (dev == NULL) {
+		printf(__FUNCTION__ ": Cannot allocate eth_device\n");
+		return (-1);
+	}
 
-        sprintf(dev->name, "ppc_4xx_eth%d", eth_num);
-        dev->priv = (void *) eth_num;
-        dev->init = ppc_4xx_eth_init;
-        dev->halt = ppc_4xx_eth_halt;
-        dev->send = ppc_4xx_eth_send;
-        dev->recv = ppc_4xx_eth_rx;
+	sprintf(dev->name, "ppc_4xx_eth%d", eth_num);
+	dev->priv = (void *) eth_num;
+	dev->init = ppc_4xx_eth_init;
+	dev->halt = ppc_4xx_eth_halt;
+	dev->send = ppc_4xx_eth_send;
+	dev->recv = ppc_4xx_eth_rx;
 
-        eth_register (dev);
+	eth_register (dev);
 }
 #else /* !defined(CONFIG_NET_MULTI) */
 void eth_halt (void)
 {
-        ppc_4xx_eth_halt(NULL);
+	ppc_4xx_eth_halt(NULL);
 }
 
 int eth_init (bd_t *bis)
 {
-        return (ppc_4xx_eth_init(NULL, bis));
+	return (ppc_4xx_eth_init(NULL, bis));
 }
 int eth_send(volatile void *packet, int length)
 {
-        return (ppc_4xx_eth_send(NULL, packet, length));
+	return (ppc_4xx_eth_send(NULL, packet, length));
 }
 
 int eth_rx(void)
 {
-        return (ppc_4xx_eth_rx(NULL));
+	return (ppc_4xx_eth_rx(NULL));
 }
 #endif /* !defined(CONFIG_NET_MULTI) */
 
diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c
index 82142a2..4b5472b 100644
--- a/cpu/ppc4xx/405gp_pci.c
+++ b/cpu/ppc4xx/405gp_pci.c
@@ -71,7 +71,6 @@
 
 #include <common.h>
 #include <command.h>
-#include <cmd_boot.h>
 #if !defined(CONFIG_440)
 #include <405gp_pci.h>
 #endif
@@ -195,7 +194,7 @@
 	/*--------------------------------------------------------------------------+
 	 * PMM2 is not used.  Initialize them to zero.
 	 *--------------------------------------------------------------------------*/
-	out32r(PMM2MA,    (pmmma[2]&~0x1)); 
+	out32r(PMM2MA,    (pmmma[2]&~0x1));
 	out32r(PMM2LA,    pmmla[2]);
 	out32r(PMM2PCILA, pmmpcila[2]);
 	out32r(PMM2PCIHA, pmmpciha[2]);
@@ -303,7 +302,7 @@
 			    struct pci_config_table *entry)
 {
 #ifdef DEBUG
-        printf("405gp_setup_bridge\n");
+	printf("405gp_setup_bridge\n");
 #endif
 }
 
@@ -409,9 +408,9 @@
 	 *--------------------------------------------------------------------------*/
     strap = mfdcr(cpc0_strp1);
     if( (strap & 0x00040000) == 0 ){
-        printf("PCI: CPC0_STRP1[PISE] not set.\n");
-        printf("PCI: Configuration aborted.\n");
-        return;
+	printf("PCI: CPC0_STRP1[PISE] not set.\n");
+	printf("PCI: Configuration aborted.\n");
+	return;
     }
 
 	/*--------------------------------------------------------------------------+
@@ -438,9 +437,9 @@
 #if defined(CFG_PCI_PRE_INIT)
     /* Let board change/modify hose & do initial checks */
     if( pci_pre_init (hose) == 0 ){
-        printf("PCI: Board-specific initialization failed.\n");
-        printf("PCI: Configuration aborted.\n");
-        return;
+	printf("PCI: Board-specific initialization failed.\n");
+	printf("PCI: Configuration aborted.\n");
+	return;
     }
 #endif
 
@@ -486,10 +485,10 @@
 	 *--------------------------------------------------------------------------*/
     if( is_pci_host(hose) ){
 #ifdef CONFIG_PCI_SCAN_SHOW
-        printf("PCI:   Bus Dev VenId DevId Class Int\n");
+	printf("PCI:   Bus Dev VenId DevId Class Int\n");
 #endif
-        out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
-        hose->last_busno = pci_hose_scan(hose);
+	out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
+	hose->last_busno = pci_hose_scan(hose);
     }
 }
 
diff --git a/cpu/ppc4xx/bedbug_405.c b/cpu/ppc4xx/bedbug_405.c
index eabc583..23752f3 100644
--- a/cpu/ppc4xx/bedbug_405.c
+++ b/cpu/ppc4xx/bedbug_405.c
@@ -5,8 +5,7 @@
 #include <common.h>
 #include <command.h>
 #include <linux/ctype.h>
-
-#include <cmd_bedbug.h>
+#include <bedbug/type.h>
 #include <bedbug/bedbug.h>
 #include <bedbug/regs.h>
 #include <bedbug/ppc.h>
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index 095a0aa..1d7c0c9 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -165,20 +165,20 @@
 	puts("IBM PowerPC 440 Rev. ");
 	switch(pvr)
 	{
-        case PVR_440GP_RB:
+	case PVR_440GP_RB:
 		putc('B');
-        /* See errata 1.12: CHIP_4 */
-        if(   ( mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0) )
-            ||( mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1) ) ){
-            puts("\n\t CPC0_SYSx DCRs corrupted. Resetting chip ...\n");
-            udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
-            do_chip_reset( mfdcr(cpc0_strp0), mfdcr(cpc0_strp1) );
-        }
+	/* See errata 1.12: CHIP_4 */
+	if(   ( mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0) )
+	    ||( mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1) ) ){
+	    puts("\n\t CPC0_SYSx DCRs corrupted. Resetting chip ...\n");
+	    udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
+	    do_chip_reset( mfdcr(cpc0_strp0), mfdcr(cpc0_strp1) );
+	}
 		break;
-        case PVR_440GP_RC:
+	case PVR_440GP_RC:
 		putc('C');
 		break;
-        default:
+	default:
 		printf("UNKNOWN (PVR=%08x)", pvr);
 		break;
 	}
@@ -192,11 +192,11 @@
 
 /* ------------------------------------------------------------------------- */
 
-int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-        /*
-         * Initiate system reset in debug control register DBCR
-         */
+	/*
+	 * Initiate system reset in debug control register DBCR
+	 */
 	__asm__ __volatile__("lis   3, 0x3000" ::: "r3");
 #if defined(CONFIG_440)
 	__asm__ __volatile__("mtspr 0x134, 3");
diff --git a/cpu/ppc4xx/i2c.c b/cpu/ppc4xx/i2c.c
index 4bf0bbd..099d30a 100644
--- a/cpu/ppc4xx/i2c.c
+++ b/cpu/ppc4xx/i2c.c
@@ -85,7 +85,7 @@
 	unsigned long freqOPB;
 	int val, divisor;
 
-#ifdef CFG_I2C_INIT_BOARD        
+#ifdef CFG_I2C_INIT_BOARD
 	/* call board specific i2c bus reset routine before accessing the   */
 	/* environment, which might be in a chip on that bus. For details   */
 	/* about this problem see doc/I2C_Edge_Conditions.                  */
@@ -134,19 +134,19 @@
 	__asm__ volatile ("eieio");
 
 
-        val = in8(IIC_MDCNTL);
-        __asm__ volatile ("eieio");
+	val = in8(IIC_MDCNTL);
+	__asm__ volatile ("eieio");
 
-        /* Ignore General Call, slave transfers are ignored,
-           disable interrupts, exit unknown bus state, enable hold
-           SCL
-           100kHz normaly or FastMode for 400kHz and above
-        */
+	/* Ignore General Call, slave transfers are ignored,
+	   disable interrupts, exit unknown bus state, enable hold
+	   SCL
+	   100kHz normaly or FastMode for 400kHz and above
+	*/
 
-        val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL;
-        if( speed >= 400000 ){
-                val |= IIC_MDCNTL_FSM;
-        }
+	val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL;
+	if( speed >= 400000 ){
+		val |= IIC_MDCNTL_FSM;
+	}
 	out8 (IIC_MDCNTL, val);
 
 	/* clear control reg */
@@ -182,153 +182,153 @@
 */
 static
 int i2c_transfer(unsigned char cmd_type,
-                 unsigned char chip,
-                 unsigned char addr[],
-                 unsigned char addr_len,
-                 unsigned char data[],
+		 unsigned char chip,
+		 unsigned char addr[],
+		 unsigned char addr_len,
+		 unsigned char data[],
 		 unsigned short data_len )
 {
-        unsigned char* ptr;
-        int reading;
-        int tran,cnt;
-        int result;
-        int status;
-        int i;
-        uchar creg;
+	unsigned char* ptr;
+	int reading;
+	int tran,cnt;
+	int result;
+	int status;
+	int i;
+	uchar creg;
 
-        if( data == 0 || data_len == 0 ){
-                /*Don't support data transfer of no length or to address 0*/
-                printf( "i2c_transfer: bad call\n" );
-                return IIC_NOK;
-        }
-        if( addr && addr_len ){
-                ptr = addr;
-                cnt = addr_len;
-                reading = 0;
-        }else{
-                ptr = data;
-                cnt = data_len;
-                reading = cmd_type;
-        }
+	if( data == 0 || data_len == 0 ){
+		/*Don't support data transfer of no length or to address 0*/
+		printf( "i2c_transfer: bad call\n" );
+		return IIC_NOK;
+	}
+	if( addr && addr_len ){
+		ptr = addr;
+		cnt = addr_len;
+		reading = 0;
+	}else{
+		ptr = data;
+		cnt = data_len;
+		reading = cmd_type;
+	}
 
-        /*Clear Stop Complete Bit*/
-        out8(IIC_STS,IIC_STS_SCMP);
-        /* Check init */
-        i=10;
-        do {
-                /* Get status */
-                status = in8(IIC_STS);
-                __asm__ volatile("eieio");
-                i--;
-        } while ((status & IIC_STS_PT) && (i>0));
+	/*Clear Stop Complete Bit*/
+	out8(IIC_STS,IIC_STS_SCMP);
+	/* Check init */
+	i=10;
+	do {
+		/* Get status */
+		status = in8(IIC_STS);
+		__asm__ volatile("eieio");
+		i--;
+	} while ((status & IIC_STS_PT) && (i>0));
 
-        if (status & IIC_STS_PT) {
-                result = IIC_NOK_TOUT;
-                return(result);
-        }
-        /*flush the Master/Slave Databuffers*/
-        out8(IIC_MDCNTL, ((in8(IIC_MDCNTL))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
-        /*need to wait 4 OPB clocks? code below should take that long*/
+	if (status & IIC_STS_PT) {
+		result = IIC_NOK_TOUT;
+		return(result);
+	}
+	/*flush the Master/Slave Databuffers*/
+	out8(IIC_MDCNTL, ((in8(IIC_MDCNTL))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
+	/*need to wait 4 OPB clocks? code below should take that long*/
 
-        /* 7-bit adressing */
-        out8(IIC_HMADR,0);
-        out8(IIC_LMADR, chip);
-        __asm__ volatile("eieio");
+	/* 7-bit adressing */
+	out8(IIC_HMADR,0);
+	out8(IIC_LMADR, chip);
+	__asm__ volatile("eieio");
 
-        tran = 0;
-        result = IIC_OK;
-        creg = 0;
+	tran = 0;
+	result = IIC_OK;
+	creg = 0;
 
-        while ( tran != cnt && (result == IIC_OK)) {
-                int  bc,j;
+	while ( tran != cnt && (result == IIC_OK)) {
+		int  bc,j;
 
-                /* Control register =
-                   Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
-                   Transfer is a sequence of transfers
-                */
-                creg |= IIC_CNTL_PT;
-
-                bc = (cnt - tran) > 4 ? 4 :
-                        cnt - tran;
-                creg |= (bc-1)<<4;
-                /* if the real cmd type is write continue trans*/
-                if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) )
-                        creg |= IIC_CNTL_CHT;
-
-                if (reading)
-                        creg |= IIC_CNTL_READ;
-                else {
-                        for(j=0; j<bc; j++) {
-                                /* Set buffer */
-                                out8(IIC_MDBUF,ptr[tran+j]);
-                                __asm__ volatile("eieio");
-                        }
-                }
-                out8(IIC_CNTL, creg );
-                __asm__ volatile("eieio");
-
-                /* Transfer is in progress
-                   we have to wait for upto 5 bytes of data
-                   1 byte chip address+r/w bit then bc bytes
-                   of data.
-                   udelay(10) is 1 bit time at 100khz
-                   Doubled for slop. 20 is too small.
+		/* Control register =
+		   Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
+		   Transfer is a sequence of transfers
 		*/
-                i=2*5*8;
-                do {
-                        /* Get status */
-                        status = in8(IIC_STS);
-                        __asm__ volatile("eieio");
-                        udelay (10);
-                        i--;
-                } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR)
+		creg |= IIC_CNTL_PT;
+
+		bc = (cnt - tran) > 4 ? 4 :
+			cnt - tran;
+		creg |= (bc-1)<<4;
+		/* if the real cmd type is write continue trans*/
+		if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) )
+			creg |= IIC_CNTL_CHT;
+
+		if (reading)
+			creg |= IIC_CNTL_READ;
+		else {
+			for(j=0; j<bc; j++) {
+				/* Set buffer */
+				out8(IIC_MDBUF,ptr[tran+j]);
+				__asm__ volatile("eieio");
+			}
+		}
+		out8(IIC_CNTL, creg );
+		__asm__ volatile("eieio");
+
+		/* Transfer is in progress
+		   we have to wait for upto 5 bytes of data
+		   1 byte chip address+r/w bit then bc bytes
+		   of data.
+		   udelay(10) is 1 bit time at 100khz
+		   Doubled for slop. 20 is too small.
+		*/
+		i=2*5*8;
+		do {
+			/* Get status */
+			status = in8(IIC_STS);
+			__asm__ volatile("eieio");
+			udelay (10);
+			i--;
+		} while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR)
 			 && (i>0));
 
-                if (status & IIC_STS_ERR) {
-                        result = IIC_NOK;
-                        status = in8 (IIC_EXTSTS);
-                        /* Lost arbitration? */
-                        if (status & IIC_EXTSTS_LA)
-                                result = IIC_NOK_LA;
-                        /* Incomplete transfer? */
-                        if (status & IIC_EXTSTS_ICT)
-                                result = IIC_NOK_ICT;
-                        /* Transfer aborted? */
-                        if (status & IIC_EXTSTS_XFRA)
-                                result = IIC_NOK_XFRA;
-                } else if ( status & IIC_STS_PT) {
-                        result = IIC_NOK_TOUT;
-                }
-                /* Command is reading => get buffer */
-                if ((reading) && (result == IIC_OK)) {
-                        /* Are there data in buffer */
-                        if (status & IIC_STS_MDBS) {
-                                /*
-                                  even if we have data we have to wait 4OPB clocks
-                                  for it to hit the front of the FIFO, after that
-                                  we can just read. We should check XFCNT here and
-                                  if the FIFO is full there is no need to wait.
+		if (status & IIC_STS_ERR) {
+			result = IIC_NOK;
+			status = in8 (IIC_EXTSTS);
+			/* Lost arbitration? */
+			if (status & IIC_EXTSTS_LA)
+				result = IIC_NOK_LA;
+			/* Incomplete transfer? */
+			if (status & IIC_EXTSTS_ICT)
+				result = IIC_NOK_ICT;
+			/* Transfer aborted? */
+			if (status & IIC_EXTSTS_XFRA)
+				result = IIC_NOK_XFRA;
+		} else if ( status & IIC_STS_PT) {
+			result = IIC_NOK_TOUT;
+		}
+		/* Command is reading => get buffer */
+		if ((reading) && (result == IIC_OK)) {
+			/* Are there data in buffer */
+			if (status & IIC_STS_MDBS) {
+				/*
+				  even if we have data we have to wait 4OPB clocks
+				  for it to hit the front of the FIFO, after that
+				  we can just read. We should check XFCNT here and
+				  if the FIFO is full there is no need to wait.
 				*/
-                                udelay (1);
-                                for(j=0;j<bc;j++) {
-                                        ptr[tran+j] = in8(IIC_MDBUF);
-                                        __asm__ volatile("eieio");
-                                }
-                        } else
-                                result = IIC_NOK_DATA;
-                }
-                creg = 0;
-                tran+=bc;
-                if( ptr == addr && tran == cnt ) {
-                        ptr = data;
-                        cnt = data_len;
-                        tran = 0;
-                        reading = cmd_type;
-                        if( reading )
-                                creg = IIC_CNTL_RPST;
-                }
-        }
-        return (result);
+				udelay (1);
+				for(j=0;j<bc;j++) {
+					ptr[tran+j] = in8(IIC_MDBUF);
+					__asm__ volatile("eieio");
+				}
+			} else
+				result = IIC_NOK_DATA;
+		}
+		creg = 0;
+		tran+=bc;
+		if( ptr == addr && tran == cnt ) {
+			ptr = data;
+			cnt = data_len;
+			tran = 0;
+			reading = cmd_type;
+			if( reading )
+				creg = IIC_CNTL_RPST;
+		}
+	}
+	return (result);
 }
 
 int i2c_probe (uchar chip)
@@ -337,89 +337,88 @@
 
 	buf[0] = 0;
 
-        /*
-         * What is needed is to send the chip address and verify that the
-         * address was <ACK>ed (i.e. there was a chip at that address which
-         * drove the data line low).
-         */
-        return(i2c_transfer (1, chip << 1, 0,0, buf, 1) != 0);
+	/*
+	 * What is needed is to send the chip address and verify that the
+	 * address was <ACK>ed (i.e. there was a chip at that address which
+	 * drove the data line low).
+	 */
+	return(i2c_transfer (1, chip << 1, 0,0, buf, 1) != 0);
 }
 
 
-
 int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
 {
-        uchar xaddr[4];
-        int ret;
+	uchar xaddr[4];
+	int ret;
 
 	if ( alen > 4 ) {
 		printf ("I2C read: addr len %d not supported\n", alen);
 		return 1;
 	}
 
-        if ( alen > 0 ) {
-                xaddr[0] = (addr >> 24) & 0xFF;
-                xaddr[1] = (addr >> 16) & 0xFF;
-                xaddr[2] = (addr >> 8) & 0xFF;
-                xaddr[3] = addr & 0xFF;
-        }
+	if ( alen > 0 ) {
+		xaddr[0] = (addr >> 24) & 0xFF;
+		xaddr[1] = (addr >> 16) & 0xFF;
+		xaddr[2] = (addr >> 8) & 0xFF;
+		xaddr[3] = addr & 0xFF;
+	}
 
 
 #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
 	/*
-         * EEPROM chips that implement "address overflow" are ones
-         * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
-         * address and the extra bits end up in the "chip address"
-         * bit slots. This makes a 24WC08 (1Kbyte) chip look like
-         * four 256 byte chips.
+	 * EEPROM chips that implement "address overflow" are ones
+	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
+	 * address and the extra bits end up in the "chip address"
+	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
+	 * four 256 byte chips.
 	 *
-         * Note that we consider the length of the address field to
-         * still be one byte because the extra address bits are
-         * hidden in the chip address.
+	 * Note that we consider the length of the address field to
+	 * still be one byte because the extra address bits are
+	 * hidden in the chip address.
 	 */
-        if( alen > 0 )
-                chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+	if( alen > 0 )
+		chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
 #endif
-        if( (ret = i2c_transfer( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
-                printf( "I2c read: failed %d\n", ret);
-                return 1;
-        }
-        return 0;
+	if( (ret = i2c_transfer( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
+		printf( "I2c read: failed %d\n", ret);
+		return 1;
+	}
+	return 0;
 }
 
 int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
 {
-        uchar xaddr[4];
+	uchar xaddr[4];
 
 	if ( alen > 4 ) {
 		printf ("I2C write: addr len %d not supported\n", alen);
 		return 1;
 
 	}
-        if ( alen > 0 ) {
-                xaddr[0] = (addr >> 24) & 0xFF;
-                xaddr[1] = (addr >> 16) & 0xFF;
-                xaddr[2] = (addr >> 8) & 0xFF;
-                xaddr[3] = addr & 0xFF;
-        }
+	if ( alen > 0 ) {
+		xaddr[0] = (addr >> 24) & 0xFF;
+		xaddr[1] = (addr >> 16) & 0xFF;
+		xaddr[2] = (addr >> 8) & 0xFF;
+		xaddr[3] = addr & 0xFF;
+	}
 
 #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
 	/*
-         * EEPROM chips that implement "address overflow" are ones
-         * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
-         * address and the extra bits end up in the "chip address"
-         * bit slots. This makes a 24WC08 (1Kbyte) chip look like
-         * four 256 byte chips.
+	 * EEPROM chips that implement "address overflow" are ones
+	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
+	 * address and the extra bits end up in the "chip address"
+	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
+	 * four 256 byte chips.
 	 *
-         * Note that we consider the length of the address field to
-         * still be one byte because the extra address bits are
-         * hidden in the chip address.
+	 * Note that we consider the length of the address field to
+	 * still be one byte because the extra address bits are
+	 * hidden in the chip address.
 	 */
-        if( alen > 0 )
-                chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+	if( alen > 0 )
+		chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
 #endif
 
-        return (i2c_transfer( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
+	return (i2c_transfer( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
 }
 
 /*-----------------------------------------------------------------------
diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c
index 0867de4..b6a956c 100644
--- a/cpu/ppc4xx/interrupts.c
+++ b/cpu/ppc4xx/interrupts.c
@@ -27,7 +27,6 @@
 #include <common.h>
 #include <watchdog.h>
 #include <command.h>
-#include <cmd_boot.h>
 #include <asm/processor.h>
 #include <ppc4xx.h>
 #include <ppc_asm.tmpl>
diff --git a/cpu/ppc4xx/kgdb.S b/cpu/ppc4xx/kgdb.S
index 78681cd..be28340 100644
--- a/cpu/ppc4xx/kgdb.S
+++ b/cpu/ppc4xx/kgdb.S
@@ -45,13 +45,13 @@
 	iccci   r0,r0		/* iccci invalidates the entire I cache */
 	/* dcache */
 	addi    r6,0,0x0000     /* clear GPR 6 */
-        addi    r7,r0, 128 	/* do loop for # of dcache lines */
+	addi    r7,r0, 128 	/* do loop for # of dcache lines */
 				/* NOTE: dccci invalidates both */
-        mtctr   r7              /* ways in the D cache */
+	mtctr   r7              /* ways in the D cache */
 ..dcloop:
-        dccci   0,r6            /* invalidate line */
-        addi    r6,r6, 32	/* bump to next line */
-        bdnz    ..dcloop
+	dccci   0,r6            /* invalidate line */
+	addi    r6,r6, 32	/* bump to next line */
+	bdnz    ..dcloop
 	blr
 
 	.globl	kgdb_flush_cache_range
diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c
index c5a90a9..0606ebe 100644
--- a/cpu/ppc4xx/miiphy.c
+++ b/cpu/ppc4xx/miiphy.c
@@ -76,7 +76,6 @@
 } /* end dump */
 
 
-
 /***********************************************************/
 /* read a phy reg and return the value with a rc           */
 /***********************************************************/
diff --git a/cpu/ppc4xx/resetvec.S b/cpu/ppc4xx/resetvec.S
index e058bf0..b3308bd 100644
--- a/cpu/ppc4xx/resetvec.S
+++ b/cpu/ppc4xx/resetvec.S
@@ -10,4 +10,3 @@
 	b _start
 #endif
 #endif
-
diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c
index e35a1d0..d4552a1 100644
--- a/cpu/ppc4xx/sdram.c
+++ b/cpu/ppc4xx/sdram.c
@@ -128,7 +128,7 @@
 	 * Now test for 64 MByte...
 	 */
 
-        /*
+	/*
 	 * Disable memory controller.
 	 */
 	mtsdram0(mem_mcopt1, 0x00000000);
@@ -179,7 +179,7 @@
 	 * Now test for 32 MByte...
 	 */
 
-        /*
+	/*
 	 * Disable memory controller.
 	 */
 	mtsdram0(mem_mcopt1, 0x00000000);
@@ -221,7 +221,7 @@
 	/*
 	 * Now test for 16 MByte...
 	 */
-        /*
+	/*
 	 * Disable memory controller.
 	 */
 	mtsdram0(mem_mcopt1, 0x00000000);
@@ -266,7 +266,7 @@
 	 * Setup for 4 MByte...
 	 */
 
-        /*
+	/*
 	 * Disable memory controller.
 	 */
 	mtsdram0(mem_mcopt1, 0x00000000);
diff --git a/cpu/ppc4xx/spd_sdram.c b/cpu/ppc4xx/spd_sdram.c
index 76aee2e..289ad12 100644
--- a/cpu/ppc4xx/spd_sdram.c
+++ b/cpu/ppc4xx/spd_sdram.c
@@ -156,7 +156,7 @@
 	 * way to minimize stack utilization.
 	 */
 #ifndef CONFIG_405EP
-    	tmp = (mfdcr(pllmd) >> (31-6)) & 0xf;	/* get FBDV bits */
+	tmp = (mfdcr(pllmd) >> (31-6)) & 0xf;	/* get FBDV bits */
 	tmp = CONFIG_SYS_CLK_FREQ * tmp;	/* get plb freq */
 #else
 	{
@@ -197,10 +197,10 @@
 #endif
 	bus_period = sdram_HZ_to_ns(tmp);	/* get sdram speed */
 
-     	/* Make shure we are using SDRAM */
+	/* Make shure we are using SDRAM */
 	if (read_spd(2) != 0x04){
-          SPD_ERR("SDRAM - non SDRAM memory module found\n");
-     	  }
+	  SPD_ERR("SDRAM - non SDRAM memory module found\n");
+	  }
 
 /*------------------------------------------------------------------
   configure memory timing register
@@ -218,17 +218,17 @@
 
 	tmp = read_spd(127) & 0x6;
      if(tmp == 0x02){      	   /* only cas = 2 supported */
-     	  min_cas = 2;
+	  min_cas = 2;
 /*     	  t_ck = read_spd(9); */
 /*     	  t_ac = read_spd(10); */
 	  }
      else if (tmp == 0x04){         /* only cas = 3 supported */
-     	  min_cas = 3;
+	  min_cas = 3;
 /*     	  t_ck = read_spd(9); */
 /*     	  t_ac = read_spd(10); */
 	  }
      else if (tmp == 0x06){         /* 2,3 supported, so use 2 */
-     	  min_cas = 2;
+	  min_cas = 2;
 /*     	  t_ck = read_spd(23); */
 /*     	  t_ac = read_spd(24); */
 	  }
@@ -292,7 +292,7 @@
 	  tmp=15625*8;
 	  break;
 	default:
-     	  SPD_ERR("SDRAM - Bad refresh period \n");
+	  SPD_ERR("SDRAM - Bad refresh period \n");
 	}
 	/* convert from nsec to bus cycles */
 	tmp = tmp/bus_period;
@@ -332,11 +332,11 @@
 	if ( (read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8) ){
 	   sdram0_ecccfg=0xf<<SDRAM0_ECCCFG_SHIFT;
 	   ecc_on = 1;
-   	}
+	}
 	else{
 	   sdram0_ecccfg=0;
 	   ecc_on = 0;
-   	}
+	}
 
 /*------------------------------------------------------------------
 	calculate total size
@@ -369,7 +369,7 @@
 			mode=0; /* mode 1 */
 			break;
 		default:
-	     	SPD_ERR("SDRAM - unsupported mode\n");
+		SPD_ERR("SDRAM - unsupported mode\n");
 		}
 		break;
 	case 12:
@@ -383,7 +383,7 @@
 			mode=1; /* mode 2 */
 			break;
 		default:
-	     	SPD_ERR("SDRAM - unsupported mode\n");
+		SPD_ERR("SDRAM - unsupported mode\n");
 		}
 		break;
 	case 13:
@@ -403,7 +403,7 @@
 			mode=2; /* mode 3 */
 			break;
 		default:
-	     	SPD_ERR("SDRAM - unsupported mode\n");
+		SPD_ERR("SDRAM - unsupported mode\n");
 		}
 		break;
 	default:
@@ -431,10 +431,10 @@
 	bank_code-=22;				/* subtract 22 to get the code */
 
 	tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1;
-    	sdram0_b0cr = (bank_size) * 0 | tmp;
-    	if(bank_cnt>1) sdram0_b2cr = (bank_size) * 1 | tmp;
-    	if(bank_cnt>2) sdram0_b1cr = (bank_size) * 2 | tmp;
-    	if(bank_cnt>3) sdram0_b3cr = (bank_size) * 3 | tmp;
+	sdram0_b0cr = (bank_size) * 0 | tmp;
+	if(bank_cnt>1) sdram0_b2cr = (bank_size) * 1 | tmp;
+	if(bank_cnt>2) sdram0_b1cr = (bank_size) * 2 | tmp;
+	if(bank_cnt>3) sdram0_b3cr = (bank_size) * 3 | tmp;
 
 
 	/*
@@ -684,34 +684,34 @@
 unsigned char spd_read(uchar chip, uint addr);
 
 void get_spd_info(unsigned long* dimm_populated,
-                  unsigned char* iic0_dimm_addr,
-                  unsigned long  num_dimm_banks);
+		  unsigned char* iic0_dimm_addr,
+		  unsigned long  num_dimm_banks);
 
 void check_mem_type
-                 (unsigned long* dimm_populated,
-                  unsigned char* iic0_dimm_addr,
-                  unsigned long  num_dimm_banks);
+		 (unsigned long* dimm_populated,
+		  unsigned char* iic0_dimm_addr,
+		  unsigned long  num_dimm_banks);
 
 void check_volt_type
-                 (unsigned long* dimm_populated,
-                  unsigned char* iic0_dimm_addr,
-                  unsigned long  num_dimm_banks);
+		 (unsigned long* dimm_populated,
+		  unsigned char* iic0_dimm_addr,
+		  unsigned long  num_dimm_banks);
 
 void program_cfg0(unsigned long* dimm_populated,
-                  unsigned char* iic0_dimm_addr,
-                  unsigned long  num_dimm_banks);
+		  unsigned char* iic0_dimm_addr,
+		  unsigned long  num_dimm_banks);
 
 void program_cfg1(unsigned long* dimm_populated,
-                  unsigned char* iic0_dimm_addr,
-                  unsigned long  num_dimm_banks);
+		  unsigned char* iic0_dimm_addr,
+		  unsigned long  num_dimm_banks);
 
 void program_rtr (unsigned long* dimm_populated,
-                  unsigned char* iic0_dimm_addr,
-                  unsigned long  num_dimm_banks);
+		  unsigned char* iic0_dimm_addr,
+		  unsigned long  num_dimm_banks);
 
 void program_tr0 (unsigned long* dimm_populated,
-                  unsigned char* iic0_dimm_addr,
-                  unsigned long  num_dimm_banks);
+		  unsigned char* iic0_dimm_addr,
+		  unsigned long  num_dimm_banks);
 
 void program_tr1 (void);
 
@@ -719,8 +719,8 @@
 
 unsigned
 long  program_bxcr(unsigned long* dimm_populated,
-                   unsigned char* iic0_dimm_addr,
-                   unsigned long  num_dimm_banks);
+		   unsigned char* iic0_dimm_addr,
+		   unsigned long  num_dimm_banks);
 
 /*
  * This function is reading data from the DIMM module EEPROM over the SPD bus
@@ -788,7 +788,7 @@
      * program the BxCR registers to find out total sdram installed
      */
     total_size = program_bxcr(dimm_populated, iic0_dimm_addr,
-        num_dimm_banks);
+	num_dimm_banks);
 
     /*
      * program SDRAM Clock Timing Register (SDRAM0_CLKTR)
@@ -810,10 +810,10 @@
      * wait for SDRAM_CFG0_DC_EN to complete
      */
     while(1) {
-        mfsdram(mem_mcsts, mcsts);
-        if ((mcsts & SDRAM_MCSTS_MRSC) != 0) {
-            break;
-        }
+	mfsdram(mem_mcsts, mcsts);
+	if ((mcsts & SDRAM_MCSTS_MRSC) != 0) {
+	    break;
+	}
     }
 
     /*
@@ -838,8 +838,8 @@
 }
 
 void get_spd_info(unsigned long*   dimm_populated,
-                  unsigned char*   iic0_dimm_addr,
-                  unsigned long    num_dimm_banks)
+		  unsigned char*   iic0_dimm_addr,
+		  unsigned long    num_dimm_banks)
 {
     unsigned long dimm_num;
     unsigned long dimm_found;
@@ -848,90 +848,90 @@
 
     dimm_found = FALSE;
     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
-        num_of_bytes = 0;
-        total_size = 0;
+	num_of_bytes = 0;
+	total_size = 0;
 
-        num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
-        total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
+	num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
+	total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 
-        if ((num_of_bytes != 0) && (total_size != 0)) {
-            dimm_populated[dimm_num] = TRUE;
-            dimm_found = TRUE;
+	if ((num_of_bytes != 0) && (total_size != 0)) {
+	    dimm_populated[dimm_num] = TRUE;
+	    dimm_found = TRUE;
 #if 0
-            printf("DIMM slot %lu: populated\n", dimm_num);
+	    printf("DIMM slot %lu: populated\n", dimm_num);
 #endif
-        }
-        else {
-            dimm_populated[dimm_num] = FALSE;
+	}
+	else {
+	    dimm_populated[dimm_num] = FALSE;
 #if 0
-            printf("DIMM slot %lu: Not populated\n", dimm_num);
+	    printf("DIMM slot %lu: Not populated\n", dimm_num);
 #endif
-        }
+	}
     }
 
     if (dimm_found == FALSE) {
-        printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
-        hang();
+	printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
+	hang();
     }
 }
 
 void check_mem_type(unsigned long*   dimm_populated,
-                    unsigned char*   iic0_dimm_addr,
-                    unsigned long    num_dimm_banks)
+		    unsigned char*   iic0_dimm_addr,
+		    unsigned long    num_dimm_banks)
 {
     unsigned long dimm_num;
     unsigned char dimm_type;
 
     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
-        if (dimm_populated[dimm_num] == TRUE) {
-            dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
-            switch (dimm_type) {
-            case 7:
+	if (dimm_populated[dimm_num] == TRUE) {
+	    dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
+	    switch (dimm_type) {
+	    case 7:
 #if 0
-                printf("DIMM slot %lu: DDR SDRAM detected\n", dimm_num);
+		printf("DIMM slot %lu: DDR SDRAM detected\n", dimm_num);
 #endif
-                break;
-            default:
-                printf("ERROR: Unsupported DIMM detected in slot %lu.\n",
-                    dimm_num);
-                printf("Only DDR SDRAM DIMMs are supported.\n");
-                printf("Replace the DIMM module with a supported DIMM.\n\n");
-                hang();
-                break;
-            }
-        }
+		break;
+	    default:
+		printf("ERROR: Unsupported DIMM detected in slot %lu.\n",
+		    dimm_num);
+		printf("Only DDR SDRAM DIMMs are supported.\n");
+		printf("Replace the DIMM module with a supported DIMM.\n\n");
+		hang();
+		break;
+	    }
+	}
     }
 }
 
 
 void check_volt_type(unsigned long*   dimm_populated,
-                     unsigned char*   iic0_dimm_addr,
-                     unsigned long    num_dimm_banks)
+		     unsigned char*   iic0_dimm_addr,
+		     unsigned long    num_dimm_banks)
 {
     unsigned long dimm_num;
     unsigned long voltage_type;
 
     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
-        if (dimm_populated[dimm_num] == TRUE) {
-            voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
-            if (voltage_type != 0x04) {
-                printf("ERROR: DIMM %lu with unsupported voltage level.\n",
-                    dimm_num);
-                hang();
-            }
-            else {
+	if (dimm_populated[dimm_num] == TRUE) {
+	    voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
+	    if (voltage_type != 0x04) {
+		printf("ERROR: DIMM %lu with unsupported voltage level.\n",
+		    dimm_num);
+		hang();
+	    }
+	    else {
 #if 0
-                printf("DIMM %lu voltage level supported.\n", dimm_num);
+		printf("DIMM %lu voltage level supported.\n", dimm_num);
 #endif
-            }
-            break;
-        }
+	    }
+	    break;
+	}
     }
 }
 
 void program_cfg0(unsigned long* dimm_populated,
-                  unsigned char* iic0_dimm_addr,
-                  unsigned long  num_dimm_banks)
+		  unsigned char* iic0_dimm_addr,
+		  unsigned long  num_dimm_banks)
 {
     unsigned long dimm_num;
     unsigned long cfg0;
@@ -951,9 +951,9 @@
      * clear bits
      */
     cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK |
-              SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD |
-              SDRAM_CFG0_DMWD_MASK |
-              SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP);
+	      SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD |
+	      SDRAM_CFG0_DMWD_MASK |
+	      SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP);
 
 
     /*
@@ -961,52 +961,52 @@
      */
     ecc_enabled = TRUE;
     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
-        if (dimm_populated[dimm_num] == TRUE) {
-            ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
-            if (ecc != 0x02) {
-                ecc_enabled = FALSE;
-            }
+	if (dimm_populated[dimm_num] == TRUE) {
+	    ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
+	    if (ecc != 0x02) {
+		ecc_enabled = FALSE;
+	    }
 
-            /*
-             * program Registered DIMM Enable
-             */
-            attributes = spd_read(iic0_dimm_addr[dimm_num], 21);
-            if ((attributes & 0x02) != 0x00) {
-                cfg0 |= SDRAM_CFG0_RDEN;
-            }
+	    /*
+	     * program Registered DIMM Enable
+	     */
+	    attributes = spd_read(iic0_dimm_addr[dimm_num], 21);
+	    if ((attributes & 0x02) != 0x00) {
+		cfg0 |= SDRAM_CFG0_RDEN;
+	    }
 
-            /*
-             * program DDR SDRAM Data Width
-             */
-            data_width =
-                (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) +
-                (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8);
-            if (data_width == 64 || data_width == 72) {
-                dimm_64bit = TRUE;
-                cfg0 |= SDRAM_CFG0_DMWD_64;
-            }
-            else if (data_width == 32 || data_width == 40) {
-                dimm_32bit = TRUE;
-                cfg0 |= SDRAM_CFG0_DMWD_32;
-            }
-            else {
-                printf("WARNING: DIMM with datawidth of %lu bits.\n",
-                    data_width);
-                printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
-                hang();
-            }
-            break;
-        }
+	    /*
+	     * program DDR SDRAM Data Width
+	     */
+	    data_width =
+		(unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) +
+		(((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8);
+	    if (data_width == 64 || data_width == 72) {
+		dimm_64bit = TRUE;
+		cfg0 |= SDRAM_CFG0_DMWD_64;
+	    }
+	    else if (data_width == 32 || data_width == 40) {
+		dimm_32bit = TRUE;
+		cfg0 |= SDRAM_CFG0_DMWD_32;
+	    }
+	    else {
+		printf("WARNING: DIMM with datawidth of %lu bits.\n",
+		    data_width);
+		printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
+		hang();
+	    }
+	    break;
+	}
     }
 
     /*
      * program Memory Data Error Checking
      */
     if (ecc_enabled == TRUE) {
-        cfg0 |= SDRAM_CFG0_MCHK_GEN;
+	cfg0 |= SDRAM_CFG0_MCHK_GEN;
     }
     else {
-        cfg0 |= SDRAM_CFG0_MCHK_NON;
+	cfg0 |= SDRAM_CFG0_MCHK_NON;
     }
 
     /*
@@ -1023,8 +1023,8 @@
 }
 
 void program_cfg1(unsigned long* dimm_populated,
-                  unsigned char* iic0_dimm_addr,
-                  unsigned long  num_dimm_banks)
+		  unsigned char* iic0_dimm_addr,
+		  unsigned long  num_dimm_banks)
 {
     unsigned long cfg1;
     mfsdram(mem_cfg1, cfg1);
@@ -1041,8 +1041,8 @@
 }
 
 void program_rtr (unsigned long* dimm_populated,
-                  unsigned char* iic0_dimm_addr,
-                  unsigned long  num_dimm_banks)
+		  unsigned char* iic0_dimm_addr,
+		  unsigned long  num_dimm_banks)
 {
     unsigned long dimm_num;
     unsigned long bus_period_x_10;
@@ -1060,36 +1060,36 @@
 
 
     for (dimm_num = 0;  dimm_num < num_dimm_banks; dimm_num++) {
-        if (dimm_populated[dimm_num] == TRUE) {
-            refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
-            switch (refresh_rate_type) {
-            case 0x00:
-                refresh_rate = 15625;
-                break;
-            case 0x011:
-                refresh_rate = 15625/4;
-                break;
-            case 0x02:
-                refresh_rate = 15625/2;
-                break;
-            case 0x03:
-                refresh_rate = 15626*2;
-                break;
-            case 0x04:
-                refresh_rate = 15625*4;
-                break;
-            case 0x05:
-                refresh_rate = 15625*8;
-                break;
-            default:
-                printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n",
-                    dimm_num);
-                printf("Replace the DIMM module with a supported DIMM.\n");
-                break;
-            }
+	if (dimm_populated[dimm_num] == TRUE) {
+	    refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
+	    switch (refresh_rate_type) {
+	    case 0x00:
+		refresh_rate = 15625;
+		break;
+	    case 0x011:
+		refresh_rate = 15625/4;
+		break;
+	    case 0x02:
+		refresh_rate = 15625/2;
+		break;
+	    case 0x03:
+		refresh_rate = 15626*2;
+		break;
+	    case 0x04:
+		refresh_rate = 15625*4;
+		break;
+	    case 0x05:
+		refresh_rate = 15625*8;
+		break;
+	    default:
+		printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n",
+		    dimm_num);
+		printf("Replace the DIMM module with a supported DIMM.\n");
+		break;
+	    }
 
-            break;
-        }
+	    break;
+	}
     }
 
     refresh_interval = refresh_rate * 10 / bus_period_x_10;
@@ -1102,8 +1102,8 @@
 }
 
 void program_tr0 (unsigned long* dimm_populated,
-                  unsigned char* iic0_dimm_addr,
-                  unsigned long  num_dimm_banks)
+		  unsigned char* iic0_dimm_addr,
+		  unsigned long  num_dimm_banks)
 {
     unsigned long dimm_num;
     unsigned long tr0;
@@ -1141,9 +1141,9 @@
      */
     mfsdram(mem_tr0, tr0);
     tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK |
-             SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
-             SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
-             SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK);
+	     SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
+	     SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
+	     SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK);
 
     /*
      * initialization
@@ -1160,83 +1160,83 @@
     tcyc_3_0_ns_x_10 = 0;
 
     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
-        if (dimm_populated[dimm_num] == TRUE) {
-            wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
-            t_rp_ns  = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
-            t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
-            t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30);
-            cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
+	if (dimm_populated[dimm_num] == TRUE) {
+	    wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
+	    t_rp_ns  = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
+	    t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
+	    t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30);
+	    cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
 
-            for (cas_index = 0; cas_index < 3; cas_index++) {
-                switch (cas_index) {
-                case 0:
-                    tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
-                    break;
-                case 1:
-                    tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
-                    break;
-                default:
-                    tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
-                    break;
-                }
+	    for (cas_index = 0; cas_index < 3; cas_index++) {
+		switch (cas_index) {
+		case 0:
+		    tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
+		    break;
+		case 1:
+		    tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
+		    break;
+		default:
+		    tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
+		    break;
+		}
 
-                if ((tcyc_reg & 0x0F) >= 10) {
-                    printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
-                        dimm_num);
-                    hang();
-                }
+		if ((tcyc_reg & 0x0F) >= 10) {
+		    printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
+			dimm_num);
+		    hang();
+		}
 
-                cycle_time_ns_x_10[cas_index] =
-                    (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F);
-            }
+		cycle_time_ns_x_10[cas_index] =
+		    (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F);
+	    }
 
-            cas_index = 0;
+	    cas_index = 0;
 
-            if ((cas_bit & 0x80) != 0) {
-                cas_index += 3;
-            }
-            else if ((cas_bit & 0x40) != 0) {
-                cas_index += 2;
-            }
-            else if ((cas_bit & 0x20) != 0) {
-                cas_index += 1;
-            }
+	    if ((cas_bit & 0x80) != 0) {
+		cas_index += 3;
+	    }
+	    else if ((cas_bit & 0x40) != 0) {
+		cas_index += 2;
+	    }
+	    else if ((cas_bit & 0x20) != 0) {
+		cas_index += 1;
+	    }
 
-            if (((cas_bit & 0x10) != 0) && (cas_index < 3)) {
-                tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
-                cas_index++;
-            }
-            else {
-                if (cas_index != 0) {
-                    cas_index++;
-                }
-                cas_3_0_available = FALSE;
-            }
+	    if (((cas_bit & 0x10) != 0) && (cas_index < 3)) {
+		tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
+		cas_index++;
+	    }
+	    else {
+		if (cas_index != 0) {
+		    cas_index++;
+		}
+		cas_3_0_available = FALSE;
+	    }
 
-            if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
-                tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index];
-                cas_index++;
-            }
-            else {
-                if (cas_index != 0) {
-                    cas_index++;
-                }
-                cas_2_5_available = FALSE;
-            }
+	    if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
+		tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index];
+		cas_index++;
+	    }
+	    else {
+		if (cas_index != 0) {
+		    cas_index++;
+		}
+		cas_2_5_available = FALSE;
+	    }
 
-            if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
-                tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
-                cas_index++;
-            }
-            else {
-                if (cas_index != 0) {
-                    cas_index++;
-                }
-                cas_2_0_available = FALSE;
-            }
+	    if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
+		tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
+		cas_index++;
+	    }
+	    else {
+		if (cas_index != 0) {
+		    cas_index++;
+		}
+		cas_2_0_available = FALSE;
+	    }
 
-            break;
-        }
+	    break;
+	}
     }
 
     /*
@@ -1245,33 +1245,33 @@
     tr0 |= SDRAM_TR0_SDWR_2_CLK;                /* Write Recovery: 2 CLK */
     switch (wcsbc) {
     case 0:
-        tr0 |= SDRAM_TR0_SDWD_0_CLK;
-        break;
+	tr0 |= SDRAM_TR0_SDWD_0_CLK;
+	break;
     default:
-        tr0 |= SDRAM_TR0_SDWD_1_CLK;
-        break;
+	tr0 |= SDRAM_TR0_SDWD_1_CLK;
+	break;
     }
 
     /*
      * Program SD_CASL field
      */
     if ((cas_2_0_available == TRUE) &&
-        (bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
-        tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
+	(bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
+	tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
     }
     else if((cas_2_5_available == TRUE) &&
-        (bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
-        tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
+	(bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
+	tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
     }
     else if((cas_3_0_available == TRUE) &&
-        (bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
-        tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
+	(bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
+	tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
     }
     else {
-        printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
-        printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
-        printf("Make sure the PLB speed is within the supported range.\n");
-        hang();
+	printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
+	printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
+	printf("Make sure the PLB speed is within the supported range.\n");
+	hang();
     }
 
     /*
@@ -1281,20 +1281,20 @@
     t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION;
     plb_check = ONE_BILLION * t_rp_clk / t_rp_ns;
     if (sys_info.freqPLB != plb_check) {
-        t_rp_clk++;
+	t_rp_clk++;
     }
     switch ((unsigned long)t_rp_clk) {
     case 0:
     case 1:
     case 2:
-        tr0 |= SDRAM_TR0_SDPA_2_CLK;
-        break;
+	tr0 |= SDRAM_TR0_SDPA_2_CLK;
+	break;
     case 3:
-        tr0 |= SDRAM_TR0_SDPA_3_CLK;
-        break;
+	tr0 |= SDRAM_TR0_SDPA_3_CLK;
+	break;
     default:
-        tr0 |= SDRAM_TR0_SDPA_4_CLK;
-        break;
+	tr0 |= SDRAM_TR0_SDPA_4_CLK;
+	break;
     }
 
     /*
@@ -1303,7 +1303,7 @@
     t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION;
     plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns);
     if (sys_info.freqPLB != plb_check) {
-        t_ras_rcd_clk++;
+	t_ras_rcd_clk++;
     }
     switch (t_ras_rcd_clk) {
     case 0:
@@ -1334,7 +1334,7 @@
     t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75);
     residue = sys_info.freqPLB % (ONE_BILLION / 75);
     if (residue >= (ONE_BILLION / 150)) {
-        t_rfc_clk++;
+	t_rfc_clk++;
     }
     switch (t_rfc_clk) {
     case 0:
@@ -1344,29 +1344,29 @@
     case 4:
     case 5:
     case 6:
-        tr0 |= SDRAM_TR0_SDRA_6_CLK;
-        break;
+	tr0 |= SDRAM_TR0_SDRA_6_CLK;
+	break;
     case 7:
-        tr0 |= SDRAM_TR0_SDRA_7_CLK;
-        break;
+	tr0 |= SDRAM_TR0_SDRA_7_CLK;
+	break;
     case 8:
-        tr0 |= SDRAM_TR0_SDRA_8_CLK;
-        break;
+	tr0 |= SDRAM_TR0_SDRA_8_CLK;
+	break;
     case 9:
-        tr0 |= SDRAM_TR0_SDRA_9_CLK;
-        break;
+	tr0 |= SDRAM_TR0_SDRA_9_CLK;
+	break;
     case 10:
-        tr0 |= SDRAM_TR0_SDRA_10_CLK;
-        break;
+	tr0 |= SDRAM_TR0_SDRA_10_CLK;
+	break;
     case 11:
-        tr0 |= SDRAM_TR0_SDRA_11_CLK;
-        break;
+	tr0 |= SDRAM_TR0_SDRA_11_CLK;
+	break;
     case 12:
-        tr0 |= SDRAM_TR0_SDRA_12_CLK;
-        break;
+	tr0 |= SDRAM_TR0_SDRA_12_CLK;
+	break;
     default:
-        tr0 |= SDRAM_TR0_SDRA_13_CLK;
-        break;
+	tr0 |= SDRAM_TR0_SDRA_13_CLK;
+	break;
     }
 
     /*
@@ -1375,20 +1375,20 @@
     t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION;
     plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns;
     if (sys_info.freqPLB != plb_check) {
-        t_rcd_clk++;
+	t_rcd_clk++;
     }
     switch (t_rcd_clk) {
     case 0:
     case 1:
     case 2:
-        tr0 |= SDRAM_TR0_SDRD_2_CLK;
-        break;
+	tr0 |= SDRAM_TR0_SDRD_2_CLK;
+	break;
     case 3:
-        tr0 |= SDRAM_TR0_SDRD_3_CLK;
-        break;
+	tr0 |= SDRAM_TR0_SDRD_3_CLK;
+	break;
     default:
-        tr0 |= SDRAM_TR0_SDRD_4_CLK;
-        break;
+	tr0 |= SDRAM_TR0_SDRD_4_CLK;
+	break;
     }
 
 #if 0
@@ -1432,19 +1432,19 @@
      */
     mfsdram(mem_tr1, tr1);
     tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK |
-             SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
+	     SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
 
     mfsdram(mem_tr0, tr0);
     if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) &&
        (sys_info.freqPLB > 100000000)) {
-        tr1 |= SDRAM_TR1_RDSS_TR2;
-        tr1 |= SDRAM_TR1_RDSL_STAGE3;
-        tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
+	tr1 |= SDRAM_TR1_RDSS_TR2;
+	tr1 |= SDRAM_TR1_RDSL_STAGE3;
+	tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
     }
     else {
-        tr1 |= SDRAM_TR1_RDSS_TR1;
-        tr1 |= SDRAM_TR1_RDSL_STAGE2;
-        tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
+	tr1 |= SDRAM_TR1_RDSS_TR1;
+	tr1 |= SDRAM_TR1_RDSL_STAGE2;
+	tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
     }
 
     /*
@@ -1474,91 +1474,91 @@
     printf("Starting memory test ");
 #endif
     for (k = 0; k < NUMHALFCYCLES; k++) {
-        for (rdclt = 0; rdclt < dly_val; rdclt++)  {
-            /*
-             * Set the timing reg for the test.
-             */
-            mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
+	for (rdclt = 0; rdclt < dly_val; rdclt++)  {
+	    /*
+	     * Set the timing reg for the test.
+	     */
+	    mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
 
-            for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
-                mtdcr(memcfga, mem_b0cr + (bxcr_num<<2));
-                if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
-                    /* Bank is enabled */
-                    membase = (unsigned long*)
-                        (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK);
+	    for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
+		mtdcr(memcfga, mem_b0cr + (bxcr_num<<2));
+		if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
+		    /* Bank is enabled */
+		    membase = (unsigned long*)
+			(mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK);
 
-                    /*
-                     * Run the short memory test
-                     */
-                    for (i = 0; i < NUMMEMTESTS; i++) {
-                        for (j = 0; j < NUMMEMWORDS; j++) {
-                            membase[j] = test[i][j];
-                            ppcDcbf((unsigned long)&(membase[j]));
-                        }
+		    /*
+		     * Run the short memory test
+		     */
+		    for (i = 0; i < NUMMEMTESTS; i++) {
+			for (j = 0; j < NUMMEMWORDS; j++) {
+			    membase[j] = test[i][j];
+			    ppcDcbf((unsigned long)&(membase[j]));
+			}
 
-                        for (j = 0; j < NUMMEMWORDS; j++) {
-                            if (membase[j] != test[i][j]) {
-                                ppcDcbf((unsigned long)&(membase[j]));
-                                break;
-                            }
-                            ppcDcbf((unsigned long)&(membase[j]));
-                        }
+			for (j = 0; j < NUMMEMWORDS; j++) {
+			    if (membase[j] != test[i][j]) {
+				ppcDcbf((unsigned long)&(membase[j]));
+				break;
+			    }
+			    ppcDcbf((unsigned long)&(membase[j]));
+			}
 
-                        if (j < NUMMEMWORDS) {
-                            break;
-                        }
-                    }
+			if (j < NUMMEMWORDS) {
+			    break;
+			}
+		    }
 
-                    /*
-                     * see if the rdclt value passed
-                     */
-                    if (i < NUMMEMTESTS) {
-                        break;
-                    }
-                }
-            }
+		    /*
+		     * see if the rdclt value passed
+		     */
+		    if (i < NUMMEMTESTS) {
+			break;
+		    }
+		}
+	    }
 
-            if (bxcr_num == MAXBXCR) {
-                if (fail_found == TRUE) {
-                    pass_found = TRUE;
-                    if (current_pass_length == 0) {
-                        current_start = rdclt_offset + rdclt;
-                    }
+	    if (bxcr_num == MAXBXCR) {
+		if (fail_found == TRUE) {
+		    pass_found = TRUE;
+		    if (current_pass_length == 0) {
+			current_start = rdclt_offset + rdclt;
+		    }
 
-                    current_fail_length = 0;
-                    current_pass_length++;
+		    current_fail_length = 0;
+		    current_pass_length++;
 
-                    if (current_pass_length > max_pass_length) {
-                        max_pass_length = current_pass_length;
-                        max_start = current_start;
-                        max_end = rdclt_offset + rdclt;
-                    }
-                }
-            }
-            else {
-                current_pass_length = 0;
-                current_fail_length++;
+		    if (current_pass_length > max_pass_length) {
+			max_pass_length = current_pass_length;
+			max_start = current_start;
+			max_end = rdclt_offset + rdclt;
+		    }
+		}
+	    }
+	    else {
+		current_pass_length = 0;
+		current_fail_length++;
 
-                if (current_fail_length >= (dly_val>>2)) {
-                    if (fail_found == FALSE) {
-                        fail_found = TRUE;
-                    }
-                    else if (pass_found == TRUE) {
-                        window_found = TRUE;
-                        break;
-                    }
-                }
-            }
-        }
+		if (current_fail_length >= (dly_val>>2)) {
+		    if (fail_found == FALSE) {
+			fail_found = TRUE;
+		    }
+		    else if (pass_found == TRUE) {
+			window_found = TRUE;
+			break;
+		    }
+		}
+	    }
+	}
 #ifdef DEBUG
-        printf(".");
+	printf(".");
 #endif
-        if (window_found == TRUE) {
-            break;
-        }
+	if (window_found == TRUE) {
+	    break;
+	}
 
-        tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
-        rdclt_offset += dly_val;
+	tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
+	rdclt_offset += dly_val;
     }
 #ifdef DEBUG
     printf("\n");
@@ -1582,10 +1582,10 @@
      */
     tr1 &= ~SDRAM_TR1_RDCD_MASK;
     if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) {
-        tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
+	tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
     }
     else {
-        tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
+	tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
     }
 
     /*
@@ -1593,21 +1593,21 @@
      */
     tr1 &= ~SDRAM_TR1_RDCT_MASK;
     while (max_end >= (dly_val<<1)) {
-        max_end -= (dly_val<<1);
-        max_start -= (dly_val<<1);
+	max_end -= (dly_val<<1);
+	max_start -= (dly_val<<1);
     }
 
     rdclt_average = ((max_start + max_end) >> 1);
     if (rdclt_average >= 0x60)
-        while(1);
+	while(1);
 
     if (rdclt_average < 0) {
-        rdclt_average = 0;
+	rdclt_average = 0;
     }
 
     if (rdclt_average >= dly_val) {
-        rdclt_average -= dly_val;
-        tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
+	rdclt_average -= dly_val;
+	tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
     }
     tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average);
 
@@ -1621,8 +1621,8 @@
 }
 
 unsigned long program_bxcr(unsigned long* dimm_populated,
-                           unsigned char* iic0_dimm_addr,
-                           unsigned long  num_dimm_banks)
+			   unsigned char* iic0_dimm_addr,
+			   unsigned long  num_dimm_banks)
 {
     unsigned long dimm_num;
     unsigned long bxcr_num;
@@ -1641,8 +1641,8 @@
      * Set the BxCR regs.  First, wipe out the bank config registers.
      */
     for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
-        mtdcr(memcfga, mem_b0cr + (bxcr_num << 2));
-        mtdcr(memcfgd, 0x00000000);
+	mtdcr(memcfga, mem_b0cr + (bxcr_num << 2));
+	mtdcr(memcfgd, 0x00000000);
     }
 
     /*
@@ -1651,106 +1651,106 @@
     bank_base_addr = CFG_SDRAM_BASE;
 
     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
-        if (dimm_populated[dimm_num] == TRUE) {
-            num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
-            num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
-            num_banks    = spd_read(iic0_dimm_addr[dimm_num], 5);
-            bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
+	if (dimm_populated[dimm_num] == TRUE) {
+	    num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
+	    num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
+	    num_banks    = spd_read(iic0_dimm_addr[dimm_num], 5);
+	    bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
 
-            /*
-             * Set the SDRAM0_BxCR regs
-             */
-            cr = 0;
-            bank_size_bytes = 4 * 1024 * 1024 * bank_size_id;
-            switch (bank_size_id) {
-            case 0x02:
-                cr |= SDRAM_BXCR_SDSZ_8;
-                break;
-            case 0x04:
-                cr |= SDRAM_BXCR_SDSZ_16;
-                break;
-            case 0x08:
-                cr |= SDRAM_BXCR_SDSZ_32;
-                break;
-            case 0x10:
-                cr |= SDRAM_BXCR_SDSZ_64;
-                break;
-            case 0x20:
-                cr |= SDRAM_BXCR_SDSZ_128;
-                break;
-            case 0x40:
-                cr |= SDRAM_BXCR_SDSZ_256;
-                break;
-            case 0x80:
-                cr |= SDRAM_BXCR_SDSZ_512;
-                break;
-            default:
-                printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
-                    dimm_num);
-                printf("ERROR: Unsupported value for the banksize: %d.\n",
-                   bank_size_id);
-                printf("Replace the DIMM module with a supported DIMM.\n\n");
-                hang();
-            }
+	    /*
+	     * Set the SDRAM0_BxCR regs
+	     */
+	    cr = 0;
+	    bank_size_bytes = 4 * 1024 * 1024 * bank_size_id;
+	    switch (bank_size_id) {
+	    case 0x02:
+		cr |= SDRAM_BXCR_SDSZ_8;
+		break;
+	    case 0x04:
+		cr |= SDRAM_BXCR_SDSZ_16;
+		break;
+	    case 0x08:
+		cr |= SDRAM_BXCR_SDSZ_32;
+		break;
+	    case 0x10:
+		cr |= SDRAM_BXCR_SDSZ_64;
+		break;
+	    case 0x20:
+		cr |= SDRAM_BXCR_SDSZ_128;
+		break;
+	    case 0x40:
+		cr |= SDRAM_BXCR_SDSZ_256;
+		break;
+	    case 0x80:
+		cr |= SDRAM_BXCR_SDSZ_512;
+		break;
+	    default:
+		printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
+		    dimm_num);
+		printf("ERROR: Unsupported value for the banksize: %d.\n",
+		   bank_size_id);
+		printf("Replace the DIMM module with a supported DIMM.\n\n");
+		hang();
+	    }
 
-            switch (num_col_addr) {
-            case 0x08:
-                cr |= SDRAM_BXCR_SDAM_1;
-                break;
-            case 0x09:
-                cr |= SDRAM_BXCR_SDAM_2;
-                break;
-            case 0x0A:
-                cr |= SDRAM_BXCR_SDAM_3;
-                break;
-            case 0x0B:
-                cr |= SDRAM_BXCR_SDAM_4;
-                break;
-            default:
-                printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
-                   dimm_num);
-                printf("ERROR: Unsupported value for number of "
-                   "column addresses: %d.\n", num_col_addr);
-                printf("Replace the DIMM module with a supported DIMM.\n\n");
-                hang();
-            }
+	    switch (num_col_addr) {
+	    case 0x08:
+		cr |= SDRAM_BXCR_SDAM_1;
+		break;
+	    case 0x09:
+		cr |= SDRAM_BXCR_SDAM_2;
+		break;
+	    case 0x0A:
+		cr |= SDRAM_BXCR_SDAM_3;
+		break;
+	    case 0x0B:
+		cr |= SDRAM_BXCR_SDAM_4;
+		break;
+	    default:
+		printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
+		   dimm_num);
+		printf("ERROR: Unsupported value for number of "
+		   "column addresses: %d.\n", num_col_addr);
+		printf("Replace the DIMM module with a supported DIMM.\n\n");
+		hang();
+	    }
 
-            /*
-             * enable the bank
-             */
-            cr |= SDRAM_BXCR_SDBE;
+	    /*
+	     * enable the bank
+	     */
+	    cr |= SDRAM_BXCR_SDBE;
 
-            /*------------------------------------------------------------------
-            | This next section is hardware dependent and must be programmed
-            | to match the hardware.
-            +-----------------------------------------------------------------*/
-            if (dimm_num == 0) {
-                for (i = 0; i < num_banks; i++) {
-                    mtdcr(memcfga, mem_b0cr + (i << 2));
-                    temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
-                                              SDRAM_BXCR_SDSZ_MASK |
-                                              SDRAM_BXCR_SDAM_MASK |
-                                              SDRAM_BXCR_SDBE);
-                    cr |= temp;
-                    cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
-                    mtdcr(memcfgd, cr);
-                    bank_base_addr += bank_size_bytes;
-                }
-            }
-            else {
-                for (i = 0; i < num_banks; i++) {
-                    mtdcr(memcfga, mem_b2cr + (i << 2));
-                    temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
-                                              SDRAM_BXCR_SDSZ_MASK |
-                                              SDRAM_BXCR_SDAM_MASK |
-                                              SDRAM_BXCR_SDBE);
-                    cr |= temp;
-                    cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
-                    mtdcr(memcfgd, cr);
-                    bank_base_addr += bank_size_bytes;
-                }
-            }
-        }
+	    /*------------------------------------------------------------------
+	    | This next section is hardware dependent and must be programmed
+	    | to match the hardware.
+	    +-----------------------------------------------------------------*/
+	    if (dimm_num == 0) {
+		for (i = 0; i < num_banks; i++) {
+		    mtdcr(memcfga, mem_b0cr + (i << 2));
+		    temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
+					      SDRAM_BXCR_SDSZ_MASK |
+					      SDRAM_BXCR_SDAM_MASK |
+					      SDRAM_BXCR_SDBE);
+		    cr |= temp;
+		    cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
+		    mtdcr(memcfgd, cr);
+		    bank_base_addr += bank_size_bytes;
+		}
+	    }
+	    else {
+		for (i = 0; i < num_banks; i++) {
+		    mtdcr(memcfga, mem_b2cr + (i << 2));
+		    temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
+					      SDRAM_BXCR_SDSZ_MASK |
+					      SDRAM_BXCR_SDAM_MASK |
+					      SDRAM_BXCR_SDBE);
+		    cr |= temp;
+		    cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
+		    mtdcr(memcfgd, cr);
+		    bank_base_addr += bank_size_bytes;
+		}
+	    }
+	}
     }
 
     return(bank_base_addr);
@@ -1775,26 +1775,26 @@
     bank_base_addr = CFG_SDRAM_BASE;
 
     if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) {
-        mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
-            SDRAM_CFG0_MCHK_GEN);
+	mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
+	    SDRAM_CFG0_MCHK_GEN);
 
-        if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) {
-            address_increment = 4;
-        }
-        else {
-            address_increment = 8;
-        }
+	if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) {
+	    address_increment = 4;
+	}
+	else {
+	    address_increment = 8;
+	}
 
-        current_address = (unsigned long)(bank_base_addr);
-        end_address = (unsigned long)(bank_base_addr) + num_bytes;
+	current_address = (unsigned long)(bank_base_addr);
+	end_address = (unsigned long)(bank_base_addr) + num_bytes;
 
-        while (current_address < end_address) {
-            *((unsigned long*)current_address) = 0x00000000;
-            current_address += address_increment;
-        }
+	while (current_address < end_address) {
+	    *((unsigned long*)current_address) = 0x00000000;
+	    current_address += address_increment;
+	}
 
-        mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
-            SDRAM_CFG0_MCHK_CHK);
+	mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
+	    SDRAM_CFG0_MCHK_CHK);
     }
 }
 
diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c
index fdefbb6..7263227 100644
--- a/cpu/ppc4xx/speed.c
+++ b/cpu/ppc4xx/speed.c
@@ -232,7 +232,7 @@
 	sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
 	sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB;
     if( get_pvr() == PVR_440GP_RB ) /* Rev B divs an extra 2 -- geez! */
-        sysInfo->freqPLB >>= 1;
+	sysInfo->freqPLB >>= 1;
 	sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
 	sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
 
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index c6a9eda..aa857d0 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -556,9 +556,9 @@
 	/*----------------------------------------------------------------------- */
 	/* DMA Status, clear to come up clean */
 	/*----------------------------------------------------------------------- */
-        addis   r3,r0, 0xFFFF         /* Clear all existing DMA status */
-        ori     r3,r3, 0xFFFF
-        mtdcr   dmasr, r3
+	addis   r3,r0, 0xFFFF         /* Clear all existing DMA status */
+	ori     r3,r3, 0xFFFF
+	mtdcr   dmasr, r3
 
 	bl	ppc405ep_init         /* do ppc405ep specific init */
 #endif /* CONFIG_405EP */
@@ -568,21 +568,21 @@
 	 * Setup OCM - On Chip Memory
 	 *******************************************************************/
 	/* Setup OCM */
- 	lis	r0, 0x7FFF
- 	ori	r0, r0, 0xFFFF
- 	mfdcr	r3, ocmiscntl 		/* get instr-side IRAM config */
- 	mfdcr	r4, ocmdscntl	/* get data-side IRAM config */
- 	and	r3, r3, r0	/* disable data-side IRAM */
- 	and	r4, r4, r0	/* disable data-side IRAM */
- 	mtdcr	ocmiscntl, r3	/* set instr-side IRAM config */
- 	mtdcr	ocmdscntl, r4	/* set data-side IRAM config */
- 	isync
+	lis	r0, 0x7FFF
+	ori	r0, r0, 0xFFFF
+	mfdcr	r3, ocmiscntl 		/* get instr-side IRAM config */
+	mfdcr	r4, ocmdscntl	/* get data-side IRAM config */
+	and	r3, r3, r0	/* disable data-side IRAM */
+	and	r4, r4, r0	/* disable data-side IRAM */
+	mtdcr	ocmiscntl, r3	/* set instr-side IRAM config */
+	mtdcr	ocmdscntl, r4	/* set data-side IRAM config */
+	isync
 
 	addis	r3, 0, CFG_OCM_DATA_ADDR@h /* OCM location */
 	mtdcr	ocmdsarc, r3
 	addis	r4, 0, 0xC000		/* OCM data area enabled */
 	mtdcr	ocmdscntl, r4
- 	isync
+	isync
 #endif
 
 	/*----------------------------------------------------------------------- */
@@ -697,7 +697,7 @@
 
 	GET_GOT			/* initialize GOT access			*/
 
-       	bl	cpu_init_f	/* run low-level CPU init code     (from Flash)	*/
+	bl	cpu_init_f	/* run low-level CPU init code     (from Flash)	*/
 
 	/* NEVER RETURNS! */
 	bl	board_init_f	/* run first part of init code (from Flash)	*/
@@ -1451,100 +1451,100 @@
 /**************************************************************************/
 #ifdef CONFIG_405EP
 ppc405ep_init:
-        /*
-        !-----------------------------------------------------------------------
-        ! Check FPGA for PCI internal/external arbitration
-        !   If board is set to internal arbitration, update cpc0_pci
-        !-----------------------------------------------------------------------
+	/*
+	!-----------------------------------------------------------------------
+	! Check FPGA for PCI internal/external arbitration
+	!   If board is set to internal arbitration, update cpc0_pci
+	!-----------------------------------------------------------------------
 	*/
-        addi    r3,0,CPC0_PCI_HOST_CFG_EN
+	addi    r3,0,CPC0_PCI_HOST_CFG_EN
 #ifdef CONFIG_BUBINGA405EP
-        addis   r5,r0,FPGA_REG1@h      /* set offset for FPGA_REG1 */
-        ori     r5,r5,FPGA_REG1@l
-        lbz     r5,0x0(r5)              /* read to get PCI arb selection */
-        andi.   r6,r5,FPGA_REG1_PCI_INT_ARB  /* using internal arbiter ?*/
-        beq     ..pci_cfg_set             /* if not set, then bypass reg write*/
+	addis   r5,r0,FPGA_REG1@h      /* set offset for FPGA_REG1 */
+	ori     r5,r5,FPGA_REG1@l
+	lbz     r5,0x0(r5)              /* read to get PCI arb selection */
+	andi.   r6,r5,FPGA_REG1_PCI_INT_ARB  /* using internal arbiter ?*/
+	beq     ..pci_cfg_set             /* if not set, then bypass reg write*/
 #endif
-        ori     r3,r3,CPC0_PCI_ARBIT_EN
+	ori     r3,r3,CPC0_PCI_ARBIT_EN
 ..pci_cfg_set:
-        mtdcr   CPC0_PCI, r3             /* Enable internal arbiter*/
+	mtdcr   CPC0_PCI, r3             /* Enable internal arbiter*/
 
-        /*
-        !-----------------------------------------------------------------------
-        ! Check to see if chip is in bypass mode.
-        ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
-        ! CPU reset   Otherwise, skip this step and keep going.
-        ! Note:  Running BIOS in bypass mode is not supported since PLB speed
-        !        will not be fast enough for the SDRAM (min 66MHz)
-        !-----------------------------------------------------------------------
+	/*
+	!-----------------------------------------------------------------------
+	! Check to see if chip is in bypass mode.
+	! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
+	! CPU reset   Otherwise, skip this step and keep going.
+	! Note:  Running BIOS in bypass mode is not supported since PLB speed
+	!        will not be fast enough for the SDRAM (min 66MHz)
+	!-----------------------------------------------------------------------
 	*/
-        mfdcr   r5, CPC0_PLLMR1
-        rlwinm  r4,r5,1,0x1            /* get system clock source (SSCS) */
-        cmpi    cr0,0,r4,0x1
+	mfdcr   r5, CPC0_PLLMR1
+	rlwinm  r4,r5,1,0x1            /* get system clock source (SSCS) */
+	cmpi    cr0,0,r4,0x1
 
-        beq    pll_done                   /* if SSCS =b'1' then PLL has */
-                                          /* already been set */
-                                          /* and CPU has been reset */
-                                          /* so skip to next section */
+	beq    pll_done                   /* if SSCS =b'1' then PLL has */
+					  /* already been set */
+					  /* and CPU has been reset */
+					  /* so skip to next section */
 
 #ifdef CONFIG_BUBINGA405EP
 	/*
-        !-----------------------------------------------------------------------
-        ! Read NVRAM to get value to write in PLLMR.
-        ! If value has not been correctly saved, write default value
-        ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
-        ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
-        !
-        ! WARNING:  This code assumes the first three words in the nvram_t
-        !           structure in openbios.h.  Changing the beginning of
-        !           the structure will break this code.
-        !
-        !-----------------------------------------------------------------------
+	!-----------------------------------------------------------------------
+	! Read NVRAM to get value to write in PLLMR.
+	! If value has not been correctly saved, write default value
+	! Default config values (assuming on-board 33MHz SYS_CLK) are above.
+	! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
+	!
+	! WARNING:  This code assumes the first three words in the nvram_t
+	!           structure in openbios.h.  Changing the beginning of
+	!           the structure will break this code.
+	!
+	!-----------------------------------------------------------------------
 	*/
-        addis   r3,0,NVRAM_BASE@h
-        addi    r3,r3,NVRAM_BASE@l
+	addis   r3,0,NVRAM_BASE@h
+	addi    r3,r3,NVRAM_BASE@l
 
-        lwz     r4, 0(r3)
-        addis   r5,0,NVRVFY1@h
-        addi    r5,r5,NVRVFY1@l
-        cmp     cr0,0,r4,r5            /* Compare 1st NVRAM Magic number*/
-        bne     ..no_pllset
-        addi    r3,r3,4
-        lwz     r4, 0(r3)
-        addis   r5,0,NVRVFY2@h
-        addi    r5,r5,NVRVFY2@l
-        cmp     cr0,0,r4,r5            /* Compare 2 NVRAM Magic number */
-        bne     ..no_pllset
-        addi    r3,r3,8                 /* Skip over conf_size */
-        lwz     r4, 4(r3)               /* Load PLLMR1 value from NVRAM */
-        lwz     r3, 0(r3)               /* Load PLLMR0 value from NVRAM */
-        rlwinm  r5,r4,1,0x1             /* get system clock source (SSCS) */
-        cmpi     cr0,0,r5,1             /* See if PLL is locked */
-        beq     pll_write
+	lwz     r4, 0(r3)
+	addis   r5,0,NVRVFY1@h
+	addi    r5,r5,NVRVFY1@l
+	cmp     cr0,0,r4,r5            /* Compare 1st NVRAM Magic number*/
+	bne     ..no_pllset
+	addi    r3,r3,4
+	lwz     r4, 0(r3)
+	addis   r5,0,NVRVFY2@h
+	addi    r5,r5,NVRVFY2@l
+	cmp     cr0,0,r4,r5            /* Compare 2 NVRAM Magic number */
+	bne     ..no_pllset
+	addi    r3,r3,8                 /* Skip over conf_size */
+	lwz     r4, 4(r3)               /* Load PLLMR1 value from NVRAM */
+	lwz     r3, 0(r3)               /* Load PLLMR0 value from NVRAM */
+	rlwinm  r5,r4,1,0x1             /* get system clock source (SSCS) */
+	cmpi     cr0,0,r5,1             /* See if PLL is locked */
+	beq     pll_write
 ..no_pllset:
 #endif /* CONFIG_BUBINGA405EP */
 
-        addis   r3,0,PLLMR0_DEFAULT@h       /* PLLMR0 default value */
-        ori     r3,r3,PLLMR0_DEFAULT@l     /* */
-        addis   r4,0,PLLMR1_DEFAULT@h       /* PLLMR1 default value */
-        ori     r4,r4,PLLMR1_DEFAULT@l     /* */
+	addis   r3,0,PLLMR0_DEFAULT@h       /* PLLMR0 default value */
+	ori     r3,r3,PLLMR0_DEFAULT@l     /* */
+	addis   r4,0,PLLMR1_DEFAULT@h       /* PLLMR1 default value */
+	ori     r4,r4,PLLMR1_DEFAULT@l     /* */
 
-        b       pll_write                 /* Write the CPC0_PLLMR with new value */
+	b       pll_write                 /* Write the CPC0_PLLMR with new value */
 
 pll_done:
-        /*
-        !-----------------------------------------------------------------------
-        ! Clear Soft Reset Register
-        ! This is needed to enable PCI if not booting from serial EPROM
-        !-----------------------------------------------------------------------
+	/*
+	!-----------------------------------------------------------------------
+	! Clear Soft Reset Register
+	! This is needed to enable PCI if not booting from serial EPROM
+	!-----------------------------------------------------------------------
 		*/
-        addi    r3, 0, 0x0
-        mtdcr   CPC0_SRR, r3
+	addi    r3, 0, 0x0
+	mtdcr   CPC0_SRR, r3
 
-        addis    r3,0,0x0010
-        mtctr   r3
+	addis    r3,0,0x0010
+	mtctr   r3
 pci_wait:
-        bdnz    pci_wait
+	bdnz    pci_wait
 
 	blr				  /* return to main code */
 
@@ -1565,43 +1565,43 @@
 !-----------------------------------------------------------------------------
 */
 pll_write:
-        mfdcr  r5, CPC0_UCR
-        andis. r5,r5,0xFFFF
-        ori    r5,r5,0x0101              /* Stop the UART clocks */
-        mtdcr  CPC0_UCR,r5               /* Before changing PLL */
+	mfdcr  r5, CPC0_UCR
+	andis. r5,r5,0xFFFF
+	ori    r5,r5,0x0101              /* Stop the UART clocks */
+	mtdcr  CPC0_UCR,r5               /* Before changing PLL */
 
-        mfdcr  r5, CPC0_PLLMR1
-        rlwinm r5,r5,0,0x7FFFFFFF        /* Disable PLL */
-        mtdcr   CPC0_PLLMR1,r5
-        oris   r5,r5,0x4000              /* Set PLL Reset */
-        mtdcr   CPC0_PLLMR1,r5
+	mfdcr  r5, CPC0_PLLMR1
+	rlwinm r5,r5,0,0x7FFFFFFF        /* Disable PLL */
+	mtdcr   CPC0_PLLMR1,r5
+	oris   r5,r5,0x4000              /* Set PLL Reset */
+	mtdcr   CPC0_PLLMR1,r5
 
-        mtdcr   CPC0_PLLMR0,r3           /* Set clock dividers */
-        rlwinm r5,r4,0,0x3FFFFFFF        /* Reset & Bypass new PLL dividers */
-        oris   r5,r5,0x4000              /* Set PLL Reset */
-        mtdcr   CPC0_PLLMR1,r5           /* Set clock dividers */
-        rlwinm r5,r5,0,0xBFFFFFFF        /* Clear PLL Reset */
-        mtdcr   CPC0_PLLMR1,r5
+	mtdcr   CPC0_PLLMR0,r3           /* Set clock dividers */
+	rlwinm r5,r4,0,0x3FFFFFFF        /* Reset & Bypass new PLL dividers */
+	oris   r5,r5,0x4000              /* Set PLL Reset */
+	mtdcr   CPC0_PLLMR1,r5           /* Set clock dividers */
+	rlwinm r5,r5,0,0xBFFFFFFF        /* Clear PLL Reset */
+	mtdcr   CPC0_PLLMR1,r5
 
 		/*
-        ! Wait min of 100us for PLL to lock.
-        ! See CMOS 27E databook for more info.
-        ! At 200MHz, that means waiting 20,000 instructions
+	! Wait min of 100us for PLL to lock.
+	! See CMOS 27E databook for more info.
+	! At 200MHz, that means waiting 20,000 instructions
 		 */
-        addi    r3,0,20000              /* 2000 = 0x4e20 */
-        mtctr   r3
+	addi    r3,0,20000              /* 2000 = 0x4e20 */
+	mtctr   r3
 pll_wait:
-        bdnz    pll_wait
+	bdnz    pll_wait
 
-        oris   r5,r5,0x8000             /* Enable PLL */
-        mtdcr   CPC0_PLLMR1,r5          /* Engage */
+	oris   r5,r5,0x8000             /* Enable PLL */
+	mtdcr   CPC0_PLLMR1,r5          /* Engage */
 
-        /*
-         * Reset CPU to guarantee timings are OK
-         * Not sure if this is needed...
- 	 */
-        addis r3,0,0x1000
-        mtspr dbcr0,r3               /* This will cause a CPU core reset, and */
-                                     /* execution will continue from the poweron */
-                                     /* vector of 0xfffffffc */
+	/*
+	 * Reset CPU to guarantee timings are OK
+	 * Not sure if this is needed...
+	 */
+	addis r3,0,0x1000
+	mtspr dbcr0,r3               /* This will cause a CPU core reset, and */
+				     /* execution will continue from the poweron */
+				     /* vector of 0xfffffffc */
 #endif /* CONFIG_405EP */
diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c
index 85f2ea4..1cf899e 100644
--- a/cpu/ppc4xx/traps.c
+++ b/cpu/ppc4xx/traps.c
@@ -203,7 +203,7 @@
 void
 ProgramCheckException(struct pt_regs *regs)
 {
-        long esr_val;
+	long esr_val;
 
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
@@ -212,12 +212,12 @@
 
 	show_regs(regs);
 
-        esr_val = get_esr();
-        if( esr_val & ESR_PIL )
+	esr_val = get_esr();
+	if( esr_val & ESR_PIL )
 		printf( "** Illegal Instruction **\n" );
-        else if( esr_val & ESR_PPR )
+	else if( esr_val & ESR_PPR )
 		printf( "** Privileged Instruction **\n" );
-        else if( esr_val & ESR_PTR )
+	else if( esr_val & ESR_PTR )
 		printf( "** Trap Instruction **\n" );
 
 	print_backtrace((unsigned long *)regs->gpr[1]);
@@ -227,15 +227,15 @@
 void
 PITException(struct pt_regs *regs)
 {
-        /*
-         * Reset PIT interrupt
-         */
-        set_tsr(0x08000000);
+	/*
+	 * Reset PIT interrupt
+	 */
+	set_tsr(0x08000000);
 
-        /*
-         * Call timer_interrupt routine in interrupts.c
-         */
-        timer_interrupt(NULL);
+	/*
+	 * Call timer_interrupt routine in interrupts.c
+	 */
+	timer_interrupt(NULL);
 }